sci-electronics/yosys
framework for Verilog RTL synthesis
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yosys-0.69~amd64+llvm_slot_21 llvm_slot_18 llvm_slot_19 llvm_slot_20
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yosys-0.69~amd64+llvm_slot_21 llvm_slot_18 llvm_slot_19 llvm_slot_20
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yosys-0.68~amd64+llvm_slot_21 llvm_slot_18 llvm_slot_19 llvm_slot_20
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USE Flags
+llvm_slot_21
* This flag is undocumented *
llvm_slot_18
* This flag is undocumented *
llvm_slot_19
* This flag is undocumented *
llvm_slot_20
* This flag is undocumented *
+abc
* This flag is undocumented *
clang
* This flag is undocumented *
+libffi
* This flag is undocumented *
+libedit
* This flag is undocumented *
readline
Global: Enables support for libreadline, a GNU line-editing library that almost everyone wants
python
Global: Adds support/bindings for the Python language
python_single_target_python3_11
* This flag is undocumented *
python_single_target_python3_12
* This flag is undocumented *
python_single_target_python3_13
* This flag is undocumented *
tcl
Global: Adds support the Tcl language
libffi
Global: use dev-libs/libffi to call native methods
libedit
Global: Use the libedit library (replacement for readline)
zlib
Global: Adds support for zlib (de)compression
test
Global: Workaround to pull in packages needed to run with FEATURES=test. Portage-2.1.2 handles this internally, so don't set it in make.conf/package.use anymore