sci-electronics/yosys
framework for Verilog RTL synthesis
USE Flags
+abc
* This flag is undocumented *
clang
* This flag is undocumented *
+libffi
* This flag is undocumented *
+libedit
* This flag is undocumented *
readline
Global: Enables support for libreadline, a GNU line-editing library that almost everyone wants
python
Global: Adds support/bindings for the Python language
python_single_target_python3_10
* This flag is undocumented *
python_single_target_python3_11
* This flag is undocumented *
python_single_target_python3_12
* This flag is undocumented *
tcl
Global: Adds support the Tcl language
libffi
Global: use dev-libs/libffi to call native methods
libedit
Global: Use the libedit library (replacement for readline)
zlib
Global: Adds support for zlib (de)compression
test
Global: Workaround to pull in packages needed to run with FEATURES=test. Portage-2.1.2 handles this internally, so don't set it in make.conf/package.use anymore
python_single_target_python3_8
* This flag is undocumented *
python_single_target_python3_9
* This flag is undocumented *