sci-electronics/yosys
framework for Verilog RTL synthesis
ChangeLog
commit 9f113f9ff5f19f3ec0e1b3c45961baa1a87bf1b0
Author: Felix Neumärker <xdch47@posteo.de>
Date: Fri Nov 29 20:54:21 2024 +0100
yosys: update
commit 05c949c22e2a7c3f89194dab01a92f6f6ae9e040
Author: Felix Neumärker <xdch47@posteo.de>
Date: Fri Nov 29 18:45:37 2024 +0100
yosys import
commit b15ed6f68dbe7bbda8908dd4894926fc09beec4b
Author: Felix Neumärker <xdch47@posteo.de>
Date: Thu Jul 7 12:55:48 2022 +0200
sci-electronics/yosys:
Package-Manager: Portage-3.0.30, Repoman-3.0.3
Signed-off-by: Felix Neumärker <xdch47@posteo.de>
commit c24657ed0d269e65632550f0c84d97dcb7bb23b3
Author: Felix Neumärker <xdch47@posteo.de>
Date: Sun Jan 31 23:22:20 2021 +0100
sci-electronics/yosys: add package
Package-Manager: Portage-3.0.14, Repoman-3.0.2
Signed-off-by: Felix Neumärker <xdch47@posteo.de>
Author: Felix Neumärker <xdch47@posteo.de>
Date: Fri Nov 29 20:54:21 2024 +0100
yosys: update
commit 05c949c22e2a7c3f89194dab01a92f6f6ae9e040
Author: Felix Neumärker <xdch47@posteo.de>
Date: Fri Nov 29 18:45:37 2024 +0100
yosys import
commit b15ed6f68dbe7bbda8908dd4894926fc09beec4b
Author: Felix Neumärker <xdch47@posteo.de>
Date: Thu Jul 7 12:55:48 2022 +0200
sci-electronics/yosys:
Package-Manager: Portage-3.0.30, Repoman-3.0.3
Signed-off-by: Felix Neumärker <xdch47@posteo.de>
commit c24657ed0d269e65632550f0c84d97dcb7bb23b3
Author: Felix Neumärker <xdch47@posteo.de>
Date: Sun Jan 31 23:22:20 2021 +0100
sci-electronics/yosys: add package
Package-Manager: Portage-3.0.14, Repoman-3.0.2
Signed-off-by: Felix Neumärker <xdch47@posteo.de>