framework for Verilog RTL synthesis
Screenshots
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yosys-0.47
~amd64 ~x86
+abc clang +libffi +libedit readline python python_single_target_python3_10 python_single_target_python3_11 python_single_target_python3_12
View Download Browse License: ISC
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yosys-0.9.3981
~amd64 ~x86
+abc clang libffi libedit readline python python_single_target_python3_8 python_single_target_python3_9 python_single_target_python3_10 python_single_target_python3_11
View Download Browse License: ISC
Reverse Dependencies
Reverse dependancies are sometimes conditional based on your USE flags, Ebuild version and sometimes other packages. please keep this in mind.