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sci-electronics/yosys

framework for Verilog RTL synthesis

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  • yosys-0.10_alpha20210918

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  • yosys-0.9
    ~amd64 ~x86
    +abc clang libffi libedit readline python python_single_target_python3_7 python_single_target_python3_8 python_single_target_python3_9

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  • yosys-0.9
    amd64

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