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sci-electronics/yosys

framework for Verilog RTL synthesis

Screenshots

  • yosys-9999

    View      Download      Browse     License: ISC   
    Overlay: salfter
  • yosys-0.56
    amd64

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    Overlay: salfter
  • yosys-0.56
    ~amd64
    +abc clang +libffi +libedit readline python python_single_target_python3_11 python_single_target_python3_12 python_single_target_python3_13

    View      Download      Browse     License: ISC   
    Overlay: xdch47
  • yosys-0.40-r1
    ~amd64

    View      Download      Browse     License: ISC   
    Overlay: guru
  • yosys-0.40
    ~amd64

    View      Download      Browse     License: ISC   
    Overlay: vowstar
  • yosys-0.32
    ~amd64

    View      Download      Browse     License: ISC   
    Overlay: vowstar
  • yosys-0.19
    ~amd64
    tcl libffi readline libedit zlib test

    View      Download      Browse     License: ISC   
    Overlay: qsx

USE Flags

+abc
* This flag is undocumented *
clang
* This flag is undocumented *
+libffi
* This flag is undocumented *
+libedit
* This flag is undocumented *
readline
Global: Enables support for libreadline, a GNU line-editing library that almost everyone wants
python
Global: Adds support/bindings for the Python language
python_single_target_python3_11
* This flag is undocumented *
python_single_target_python3_12
* This flag is undocumented *
python_single_target_python3_13
* This flag is undocumented *
tcl
Global: Adds support the Tcl language
libffi
Global: use dev-libs/libffi to call native methods
libedit
Global: Use the libedit library (replacement for readline)
zlib
Global: Adds support for zlib (de)compression
test
Global: Workaround to pull in packages needed to run with FEATURES=test. Portage-2.1.2 handles this internally, so don't set it in make.conf/package.use anymore