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sci-electronics/yosys

framework for Verilog RTL synthesis

Screenshots

  • yosys-9999

    View      Download      Browse     License: ISC   
    Overlay: salfter
  • yosys-0.55
    amd64

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    Overlay: salfter
  • yosys-0.47
    ~amd64 ~x86
    +abc clang +libffi +libedit readline python python_single_target_python3_10 python_single_target_python3_11 python_single_target_python3_12

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    Overlay: xdch47
  • yosys-0.40-r1
    ~amd64

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    Overlay: guru
  • yosys-0.40
    ~amd64

    View      Download      Browse     License: ISC   
    Overlay: vowstar
  • yosys-0.32
    ~amd64

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    Overlay: vowstar
  • yosys-0.19
    ~amd64
    tcl libffi readline libedit zlib test

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    Overlay: qsx
  • yosys-0.9.3981
    ~amd64 ~x86
    +abc clang libffi libedit readline python python_single_target_python3_8 python_single_target_python3_9 python_single_target_python3_10 python_single_target_python3_11

    View      Download      Browse     License: ISC   
    Overlay: xdch47

Reverse Dependencies

sci-electronics/amaranth
Reverse dependancies are sometimes conditional based on your USE flags, Ebuild version and sometimes other packages. please keep this in mind.