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sci-electronics/yosys

framework for Verilog RTL synthesis

Screenshots

  • yosys-0.10_alpha20210601

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    Overlay: salfter
  • yosys-0.9
    ~amd64 ~x86
    +abc clang libffi libedit readline python python_single_target_python3_7 python_single_target_python3_8 python_single_target_python3_9

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    Overlay: xdch47
  • yosys-0.9
    amd64

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    Overlay: salfter

ChangeLog

commit c24657ed0d269e65632550f0c84d97dcb7bb23b3
Author: Felix Neumärker <xdch47@posteo.de>
Date: Sun Jan 31 23:22:20 2021 +0100

sci-electronics/yosys: add package

Package-Manager: Portage-3.0.14, Repoman-3.0.2
Signed-off-by: Felix Neumärker <xdch47@posteo.de>