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sci-electronics/yosys

framework for Verilog RTL synthesis

Screenshots

  • yosys-0.71
    ~amd64

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    Overlay: salfter
  • yosys-0.69
    ~amd64
    +llvm_slot_21 llvm_slot_18 llvm_slot_19 llvm_slot_20

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    Overlay: vowstar
  • yosys-0.69
    ~amd64
    +llvm_slot_21 llvm_slot_19 llvm_slot_20

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    Overlay: guru
  • yosys-0.68
    ~amd64
    +llvm_slot_21 llvm_slot_19 llvm_slot_20

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    Overlay: guru
  • yosys-0.56
    ~amd64
    +abc clang +libffi +libedit readline python python_single_target_python3_11 python_single_target_python3_12 python_single_target_python3_13

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    Overlay: xdch47
  • yosys-0.19
    ~amd64
    tcl libffi readline libedit zlib test

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    Overlay: qsx

Bugs

Bug # Severity Platform Status Description
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