Gentoo Portage Overlays - sci-electronics/yosys

sci-electronics/yosys

Framework for Verilog RTL synthesis

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http://www.clifford.at/yosys/

yosys-0.9.3981

~amd64 ~x86

+abc clang libffi libedit readline python python_single_target_python3_8 python_single_target_python3_9 python_single_target_python3_10 python_single_target_python3_11

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Browse License: ISC

Overlay: xdch47

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