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sci-electronics/yosys

framework for Verilog RTL synthesis

Screenshots

  • yosys-0.69
    ~amd64
    +llvm_slot_21 llvm_slot_19 llvm_slot_20

    View      Download      Browse     License: ISC   
    Overlay: guru
  • yosys-0.68
    ~amd64
    +llvm_slot_21 llvm_slot_19 llvm_slot_20

    View      Download      Browse     License: ISC   
    Overlay: guru