sci-electronics/qsoc
Quick System on Chip Studio for SoC design and Verilog code generation
ChangeLog
commit a89b95d2f5c7d0cc5b349151328872fbcfa02cf1
Author: Huang Rui <vowstar@gmail.com>
Date: Wed Oct 7 21:55:00 2026 -0700
sci-electronics/qsoc: add 2.7.2, drop 2.7.1
Signed-off-by: Huang Rui <vowstar@gmail.com>
commit 936ce90bc6aac6f973e59f05992bc4a6a966901a
Author: Huang Rui <vowstar@gmail.com>
Date: Wed Oct 7 02:33:14 2026 -0700
sci-electronics/qsoc: add 2.7.1, drop 2.7.0
Signed-off-by: Huang Rui <vowstar@gmail.com>
commit 7b6af6bc79f212df69249adb6e63c3c3f7821b39
Author: Huang Rui <vowstar@gmail.com>
Date: Sun Oct 4 06:51:52 2026 -0700
sci-electronics/qsoc: new package, add 2.7.0
Signed-off-by: Huang Rui <vowstar@gmail.com>
Author: Huang Rui <vowstar@gmail.com>
Date: Wed Oct 7 21:55:00 2026 -0700
sci-electronics/qsoc: add 2.7.2, drop 2.7.1
Signed-off-by: Huang Rui <vowstar@gmail.com>
commit 936ce90bc6aac6f973e59f05992bc4a6a966901a
Author: Huang Rui <vowstar@gmail.com>
Date: Wed Oct 7 02:33:14 2026 -0700
sci-electronics/qsoc: add 2.7.1, drop 2.7.0
Signed-off-by: Huang Rui <vowstar@gmail.com>
commit 7b6af6bc79f212df69249adb6e63c3c3f7821b39
Author: Huang Rui <vowstar@gmail.com>
Date: Sun Oct 4 06:51:52 2026 -0700
sci-electronics/qsoc: new package, add 2.7.0
Signed-off-by: Huang Rui <vowstar@gmail.com>


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