sci-electronics/abc
ABC: System for Sequential Logic Synthesis and Formal Verification
ChangeLog
commit 9a2c292706f8e5823712f785d271ee2a9cb46f7f
Author: Thomas Schneider <qsx@chaotikum.eu>
Date: Wed Jul 27 17:21:20 2022 +0200
sci-electronics/abc: Add ebuild
Author: Thomas Schneider <qsx@chaotikum.eu>
Date: Wed Jul 27 17:21:20 2022 +0200
sci-electronics/abc: Add ebuild